This invention relates to computer system architectures and more particularly to a microprocessor system having a system bus for coupling system elements, and having a dual bus microprocessor with separate instruction and data cache interfaces coupled to independently operable instruction and data caches which are coupled to the system bus.
Prior microprocessor system architectures have provided a single external cache subsystem for data and/or instructions. Such systems have typically provided for direct microprocessor interface to both the cache system and other system elements. In prior systems, a single address/data/control bus provided for interfacing to the cache system and to other system elements. Some newer microprocessor designs have provided a separate interface to a single cache system for data and/or instructions. Some have additionally provided a separate general bus for coupling of all system elements to the microprocessor, including main memory, peripheral controller chips, etc. Transfer of digital information to and from the microprocessor in these prior art designs could either occur between microprocessor and the cache system or the microprocessor and peripheral controllers or main memory directly. Furthermore, the cache system memory cycle required address information from the processor to the cache system for each transfer of digital information to the processor from the cache system. While the cache system could return one or more words of data per cache system data transfer, each cache system memory access cycle required a separate address be provided from the processor.